Field
Embodiments described herein generally relate to the fabrication of integrated circuits (ICs), and more particularly, to methods for selective deposition of carbon structures.
Description of the Related Art
Reducing the size of ICs results in improved performance, increased capacity and/or reduced cost. Each size reduction requires more sophisticated techniques to form the ICs. Photolithography is commonly used to pattern ICs on a substrate. With the critical dimensions of advanced nodes of semiconductor devices and structures continuing to shrink, managing multiple mask passes per device layer and edge placement error (EPE) associated with multiple passes have become the biggest challenges to next generation lithography. Processes such as self-aligned double patterning (SADP), self-aligned quad patterning (SAQP), and litho-etch-litho-etch (LELE) may be used for extending the capabilities of photolithographic techniques beyond the minimum pitch capabilities of existing lithographic equipment. Following the SADP, SAQP, or LELE process, multi-cut or block masks are placed over the lines and spaces generated by SADP, SAQP, or LELE process to perform device patterning. As the feature size decreases, pitch and linewidth also decrease, causing the mask edge placement control to be more complicated and difficult.
Therefore, an improved method is needed.